Asynchronous FIFO

Table 1. Asynchronous FIFO Write Flags Update Latency Due to wr_en_i
Port Latency (PIPELINE_REG=0) Latency (PIPELINE_REG=1)
wr_ack_o 0 0
full_o 0 0
almost_full_o 0 0
prog_full_o 0 0
overflow_o 0 0
wr_datacount_o 0 0
Table 2. Asynchronous FIFO Read Flags Update Latency Due to wr_en_i
Port Latency (PIPELINE_REG=0) Latency (PIPELINE_REG=1)
rd_valid_o – –
empty_o 1 wr_clk_i + 2 rd_clk_i 1 wr_clk_i + 3 rd_clk_i
almost_empty_o 1 wr_clk_i + 2 rd_clk_i 1 wr_clk_i + 3 rd_clk_i
prog_empty_o 1 wr_clk_i + 2 rd_clk_i 1 wr_clk_i + 3 rd_clk_i
underflow_o – –
rd_datacount_o 1 wr_clk_i + 2 rd_clk_i 1 wr_clk_i + 3 rd_clk_i
Table 3. Asynchronous FIFO Write Flags Update Latency Due to rd_en_i
Port Latency (PIPELINE_REG=0) Latency (PIPELINE_REG=1)
wr_ack_o – –
full_o 1 rd_clk_i + 2 wr_clk_i 1 rd_clk_i + 3 wr_clk_i
almost_full_o 1 rd_clk_i + 2 wr_clk_i 1 rd_clk_i + 3 wr_clk_i
prog_full_o 1 rd_clk_i + 2 wr_clk_i 1 rd_clk_i + 3 wr_clk_i
overflow_o – –
wr_datacount_o 1 rd_clk_i + 2 wr_clk_i 1 rd_clk_i + 3 wr_clk_i
Table 4. Asynchronous FIFO Read Flags Update Latency Due to rd_en_i
Port Latency (PIPELINE_REG=0) Latency (PIPELINE_REG=1)
rd_valid_o 01 01
empty_o 0 0
almost_empty_o 0 0
prog_empty_o 0 0
underflow_o 0 0
rd_datacount_o 0 0
1 OUTPUT_REG adds one latency to these signal.