Efinix, Inc.
  • Introduction
  • Features
  • Device Support
  • Resource Utilization and Performance
  • Release Notes
  • Functional Description
    • Ports
    • Synchronous FIFO Operation
    • Asynchronous FIFO Operation
    • Asymmetric Width Operation
    • Overflow or Underflow Protection
    • Programmable Full and Empty Signals
    • Reset
    • Datacount
    • Timing Constraints (SDC)
      • LUT Register Mode
      • Asynchronous FIFO
    • Latency
      • Synchronous FIFO
      • Asynchronous FIFO
  • IP Manager
  • Customizing the FIFO
  • FIFO Example Design
  • FIFO Testbench
  • Revision History

Timing Constraints (SDC)

This section details the specific timing constraints required to ensure reliable operation of the FIFO IP.

  • LUT Register Mode
  • Asynchronous FIFO
Parent topic: Functional Description

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