FIFO Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Optional Signals option must be enabled.

Important: Efinix tested the example design generated with default parameters and the Optional Signals option enabled.

The example design targets the Trion® T20 BGA256 Development Board. The design demonstrates the continuous read-write operation using both symmetric and asymmetric width FIFO as well as using FIFO status signal as part of the read write control operation.

The data generator produces continuous 16-bit incremental data once the system reset is release. The 16-bit data is directly written into the asymmetric FIFO (configured as 1:2 ratio including asynchronous clock settings). The same 16-bit data goes through the data accumulator block to assemble a 32-bit data before written into the symmetric FIFO. This process is to ensure that the write and read data has a 1:1 ratio.

Both FIFO read operations are triggered only after prog_full_o signal of asymmetric FIFO is asserted. The programmable full threshold is set to a quarter of the total write depth. The FIFO read-write operation can run continuously without hitting FIFO full / FIFO empty due to:

The FIFO write clock is running two times faster than the read clock
Both write and read clock is generated from the same PLL (0 PPM)

In order to observe asymmetric FIFO full or empty behavior, you can trigger a stop read or stop write to interrupt the FIFO read / write operation through the pushbuttons.

Table 1. Example Design Input and Output
Input / Output	Description
LED D3	Upon power-up, LED D3 blinks continuously to indicate that the design is running on the board.
LED D4	Turns on when there is read data error during comparison. Pressing SW5 / SW6 button can also cause read data comparison error.
LED D5	Turns on when asymmetric FIFO is full. Occurs when pressing SW6 pushbutton.
LED D6	Turns on when asymmetric FIFO is empty. Occurs when pressing SW5 pushbutton.
Pushbutton SW4	System reset. Use system reset to clear read comparison error.
Pushbutton SW5	Stop write. Triggers a stop write and causes the asymmetric FIFO to hit full status.
Pushbutton SW6	Stop read. Triggers a stop read and causes the asymmetric FIFO to hit empty status.

Table 2. Titanium Asynchronous Example Design Implementation
FPGA	Mode	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Block	DSP Block	f_MAX (MHz)^¹		Efinity Version^²
FPGA	Mode	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Block	DSP Block	wr_clk_i	rd_clk_i	Efinity Version^²
Ti60 F225 C4	Standard	334/60800 (0.07%)	4/256 (2%)	0/160 (0%)	416.84	262.74	2023.2
Ti60 F225 C4	FWFT	351/60800 (0.1%)	4/256 (2%)	0/160 (0%)	431.22	259.67	2023.2

Table 3. Trion® Example Design Implementation
FPGA	Mode	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Block	DSP Block	f_MAX (MHz)^¹		Efinity Version^²
FPGA	Mode	Logic Elements (Logic, Adders, Flipflops, etc.)	Memory Block	DSP Block	wr_clk_i	rd_clk_i	Efinity Version^²
T20 F256 C4	Standard	354/19728(2%)	2/204 (3%)	0/36 (0%)	155.06	134.48	2023.2
T20 F256 C4	FWFT	371/19728 (2%)	2/204 (3%)	0/36 (0%)	157.73	117.63	2023.2