Features

  • Depths up to 131,072 words
  • Data widths from 1 to 512 bits
  • Symmetric or non-symmetric aspect ratios (read-to-write port ratios ranging from 1:16 to 16:1)
  • Synchronous or asynchronous clock domains supports standard or First–Word–Fall–Through (FWFT)
  • Programmable full and empty status flags, set by user–defined parameters
  • Almost full and almost empty flags indicate one word left
  • Configurable handshake signals
  • Asynchronous clock domain FWFT read mode
  • FIFO datacount to indicate how many words available in FIFO
  • Option to exclude optional flags
  • Option to exclude overflow and underflow protection
  • Includes example designs targeting the Trion® T20 BGA256 Development Board
  • Verilog RTL and simulation testbench