Introduction

Note: The FIFO is available in the Efinity software v2021.1.165 with patch v2021.1.165.2.19 or higher. The FIFO (Legacy) is obsoleted and replaced with FIFO in Efinity software v2021.2. You cannot migrate automatically from the FIFO (Legacy) to the FIFO. Therefore, Efinix® recommends that you use the FIFO for all new designs. You can continue to use FIFO (Legacy) with the Efinity software v2021.1.165 or lower. However, the FIFO will not be supported in future Efinity releases.

Note: If you had generated the FIFO IP using versions 2024.1.163, 2024.1.163.1.8, or 2024.1.163.2.15, or if you had migrated your project to any of these versions with Programmable Full Feature or Optional Signals enabled, you must regenerate the IP using the latest Efinity version. Otherwise, you can ignore this warning.

Note: When migrating the FIFO IP from version 2023.2.307 or lower, the overflow protection and underflow settings are linked to the Optional Signals configuration. You can Enabled or Disabled these features (first introduced since version 2024.1.163). If the default settings do not align with your design intent, you can adjust the overflow protection and underflow protection options in the GUI and regenerate the IP.

The FIFO core is a customizable first-in first-out memory queue that uses block RAM in the FPGA for storage. The core has parameters you use to create a custom instance. For example, you can set the FIFO depth, the data bus width, whether the read and write domains are synchronous or asynchronous, etc.

Use the IP Manager to select IP, customize it, and generate files. The FIFO core has an interactive wizard to help you set parameters. The wizard also has options to create a testbench and/or example design targeting an Efinix® development board.