Overflow or Underflow Protection

The overflow protection disables the wr_en_i port when the FIFO is full, while the underflow protection disables the rd_en_i port when the FIFO is empty. The function of this feature is to prevent overflowing or underflowing the FIFO, thus preventing any destruction to the contents stored in the FIFO.

To achieve better timing performance, you can choose to disable this feature. While disabling this feature, your logic must ensure no overflowing or underflowing on the FIFO by monitoring the almost_full_o or almost_empty_o signals. These signals are available once you select Optional Signals > Enable in IP Configuration.

Note: The consequences of overflowing or underflowing are unpredictable. As a result, all the output signals may not function as per the design intent, except for the following output signals:
  • overflow_o
  • underflow_o
If an overflow or underflow happens, the overflow_o or underflow_o port remains asserted and is required to trigger a reset.
Figure 1. Synchronous Standard Mode FIFO Overflow with OUTPUT_REG = 0 and OVERFLOW_PROTECT = 0
Figure 2. Synchronous Standard Mode FIFO Overflow with OUTPUT_REG = 0, OVERFLOW_PROTECT = 1, and UNDERFLOW_PROTECT = 0