Note: The resources and performance values provided are based on some
of the supported FPGAs. These values are just guidance and may change depending on the
device resource utilization, design congestion, and user design.
The following timing data are based on default settings with overflow protection and
underflow protection disabled.
Titanium Resource Utilization and Performance
Table 1. Synchronous Clock FIFO
| FPGA |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops, etc.) |
Memory Block |
DSP Block |
fMAX (MHz)1 |
Efinity Version2 |
| Ti60 F225 C4 |
Standard |
1:1 |
44/60800 (0.07%) |
1/256 (0.4%) |
0/160 (0%) |
600 |
2023.2 |
| 1:2 |
44/60800 (0.07%) |
2/256 (0.8%) |
0/160 (0%) |
600 |
| FWFT |
1:1 |
70/60800 (0.1%) |
1/256 (0.4%) |
0/160 (0%) |
600 |
| 1:2 |
65/60800 (0.1%) |
2/256 (0.8%) |
0/160 (0%) |
600 |
Table 2. Asynchronous Clock FIFO
| FPGA |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops,
etc.) |
Memory Block |
DSP Block |
fMAX (MHz)1 |
Efinity Version2 |
| wr_clk_i |
rd_clk_i |
| Ti60 F225 C4 |
Standard |
1:1 |
147/60800 (0.07%) |
1/256 (0.4%) |
0/160 (0%) |
600 |
600 |
2023.2 |
| 1:2 |
139/60800 (0.07%) |
2/256 (0.8%) |
0/160 (0%) |
600 |
350 |
| FWFT |
1:1 |
189/60800 (0.1%) |
1/256 (0.4%) |
0/160 (0%) |
600 |
600 |
| 1:2 |
174/60800 (0.1%) |
2/256 (0.8%) |
0/160 (0%) |
600 |
350 |
Table 3. Synchronous Clock FIFO (LUT Register Implementation)
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops, etc.) |
Memory Block |
DSP Block |
fMAX (MHz)1 |
Efinity Version2 |
| Ti60 F225 C4 |
Synchronous |
Standard |
1:2 |
464/60800 (0.76%) |
0/256 (0%) |
0/160 (0%) |
600 |
2024.1 |
| FWFT |
1:2 |
507/60800 (0.83%) |
0/256 (0%) |
0/160 (0%) |
600 |
Table 4. Asynchronous Clock FIFO (LUT Register Implementation)
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops,
etc.) |
Memory Block |
DSP Block |
fMAX (MHz)3 |
Efinity Version4 |
| wr_clk_i |
rd_clk_i |
| Ti60 F225 C4 |
Asynchronous |
Standard |
1:2 |
509/60800 (0.84%) |
0/256 (0%) |
0/160 (0%) |
600 |
300 |
2024.1 |
| FWFT |
1:2 |
533/60800 (0.88%) |
0/256 (0%) |
0/160 (0%) |
600 |
300 |
Trion Resource Utilization and Performance
Table 5. Synchronous Clock FIFO
| FPGA |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops, etc.) |
Memory Block |
DSP Block |
fMAX (MHz)3 |
Efinity Version4 |
| T20 F256 C4 |
Standard |
1:1 |
44/19728 (0.2%) |
2/204 (1%) |
0/36 (0%) |
200 |
2023.2 |
| 1:2 |
41/19728(0.2%) |
2/204(1%) |
0/36 (0%) |
200 |
| FWFT |
1:1 |
70/19728 (0.4%) |
2/204 (1%) |
0/36 (0%) |
200 |
| 1:2 |
65/19728 (0.3%) |
2/204 (1%) |
0/36 (0%) |
200 |
Table 6. Asynchronous Clock FIFO
| FPGA |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops,
etc.) |
Memory Block |
DSP Block |
fMAX (MHz)3 |
Efinity Version4 |
| wr_clk_i |
rd_clk_i |
| T20 F256 C4 |
Standard |
1:1 |
147/19728(0.7%) |
2/204 (1%) |
0/36 (0%) |
200 |
200 |
2023.2 |
| 1:2 |
139/19728 (0.7%) |
2/204 (1%) |
0/36 (0%) |
200 |
200 |
| FWFT |
1:1 |
189/19728 (1.0%) |
2/204 (1%) |
0/36 (0%) |
200 |
200 |
| 1:2 |
174/19728 (0.8%) |
2/204 (1%) |
0/36 (0%) |
200 |
200 |
Table 7. Synchronous Clock FIFO (LUT Register Implementation)
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops, etc.) |
Memory Block |
DSP Block |
fMAX (MHz)3 |
Efinity Version4 |
| T20 F256 C4 |
Synchronous |
Standard |
1:2 |
464/19728 (2.35%) |
0/204 (0%) |
0/36 (0%) |
200 |
2024.1 |
| FWFT |
1:2 |
507/19728 (2.57%) |
0/204 (0%) |
0/36 (0%) |
200 |
Table 8. Asynchronous Clock FIFO (LUT Register Implementation)
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops,
etc.) |
Memory Block |
DSP Block |
fMAX (MHz)5 |
Efinity Version6 |
| wr_clk_i |
rd_clk_i |
| T20 F256 C4 |
Asynchronous |
Standard |
1:2 |
509/19728 (2.58%) |
0/204 (0%) |
0/36 (0%) |
200 |
100 |
2024.1 |
| FWFT |
1:2 |
533/19728 (2.70%) |
0/204 (0%) |
0/36 (0%) |
200 |
100 |
Topaz Resource Utilization and Performance
Table 9. Synchronous Clock FIFO
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops, etc.) |
Memory Block |
DSP Block |
fMAX (MHz)5 |
Efinity Version6 |
| Tz50 F225 |
Synchronous |
Standard |
1:1 |
46/55786 (0.08%) |
1/235 (0.43%) |
0/140 (0%) |
450 |
2024.2 |
| 1:2 |
43/55786 (0.08%) |
2/235 (0.85%) |
0/140 (0%) |
450 |
| FWFT |
1:1 |
73/55786 (0.13%) |
1/235 (0.43%) |
0/140 (0%) |
450 |
| 1:2 |
67/55786 (0.12%) |
2/235 (0.85%) |
0/140 (0%) |
450 |
Table 10. Asynchronous Clock FIFO
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops,
etc.) |
Memory Block |
DSP Block |
fMAX (MHz)7 |
Efinity Version8 |
| wr_clk_i |
rd_clk_i |
| Tz50 F255 |
Asynchronous |
Standard |
1:1 |
151/55786 (0.27%) |
1/235 (0.43%) |
0/140 (0%) |
450 |
450 |
2024.2 |
| 1:2 |
138/55786 (0.25%) |
2/235 (0.85%) |
0/140 (0%) |
450 |
225 |
| FWFT |
1:1 |
151/55786 (0.27%) |
1/235 (0.43%) |
0/140 (0%) |
450 |
450 |
| 1:2 |
138/55786 (0.25%) |
2/235 (0.85%) |
0/140 (0%) |
450 |
225 |
Table 11. Synchronous Clock FIFO (LUT Register Implementation)
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops, etc.) |
Memory Block |
DSP Block |
fMAX (MHz)7 |
Efinity Version8 |
| Tz50 F225 |
Synchronous |
Standard |
1:2 |
462/55786 (0.83%) |
0/235 (0%) |
0/140 (0%) |
450 |
2024.2 |
| FWFT |
1:2 |
504/55786 (0.9%) |
0/235 (0%) |
0/140 (0%) |
450 |
Table 12. Asynchronous Clock FIFO (LUT Register Implementation)
| FPGA |
Clock Mode |
Mode |
Asymmetric Width Ratio |
Logic Elements (Logic, Adders, Flipflops,
etc.) |
Memory Block |
DSP Block |
fMAX (MHz)7 |
Efinity Version8 |
| wr_clk_i |
rd_clk_i |
| Tz50 F225 |
Synchronous |
Standard |
1:2 |
502/55786 (0.9%) |
0/235 (0%) |
0/140 (0%) |
450 |
225 |
2024.2 |
| FWFT |
1:2 |
537/55786 (0.96%) |
0/235 (0%) |
0/140 (0%) |
450 |
225 |