Reset

The FIFO core uses active high asynchronous reset. By default, the reset signal (a_rst_i) is synchronized to the respective clock domains before being used in the core logic. You must ensure that the rst_busy signal is low before the start of any FIFO operations. Note that the rst_busy signal is asynchronous, and must be synchronized to the respective clock domain to use it.

If the reset synchronization is already included in the user logic, you can bypass the reset synchronizer logic in FIFO core by selecting Reset Synchronizer > Disable in the IP Configuration window. In this scenario, you must directly connect a_wr_rst_i and a_rd_rst_i ports.