Ports
| Port | Synchronous | Asynchronous | Direction | Description |
|---|---|---|---|---|
| a_rst_i |  |
|
Input | Reset. Asynchronous reset signal that initializes all internal pointers and output flags. |
| a_wr_rst_i | |
Input | The incoming reset signal should already synchronized to the write clock domain. This signal is exposed when Reset Synchronizer option is disabled in the IP Configuration window. | |
| a_rd_rst_i | |
Input | The incoming reset signal should already synchronized to the read clock domain. This signal is exposed when Reset Synchronizer option is disabled in the IP Configuration window. | |
| rst_busy | |
Output | When asserted, this signal indicate the core is being reset. This signal is asynchronous. You should synchronized it to the respective clock domain before use. This signal is exposed when Reset Synchronizer option is enabled in the IP Configuration window. | |
| wr_clk_i | |
Input | Write clock. All signals in the write domain are synchronous to this clock. | |
| rd_clk_i | |
Input | Read clock. All signals in the read domain are synchronous to this clock. | |
| clk_i | |
Input | Clock. All signals on the write and read domains are synchronous to this clock. | |
| wr_datacount_o [n:0] | |
|
Output | FIFO write domain data count. Applicable to asymmetric width
ratio. n=log2[DEPTH]. |
| rd_datacount_o [n:0] | |
|
Output | FIFO read domain data count. Applicable to asymmetric width
ratio. n=log2[DEPTH]. |
| datacount_o [n:0] | |
Output | FIFO data count. Applicable to symmetric width
ratio. n=log2[DEPTH]. |
| Port | Direction | Description |
|---|---|---|
| wdata [m-1:0] | Input | Write data. The input data bus used when writing to the FIFO
buffer. m=DATA_WIDTH. |
| wr_en_i | Input | Write enable. If the FIFO buffer is not full, asserting this signal causes data (on wdata) to be written to the FIFO. |
| full_o | Output | Full flag. When asserted, this signal indicates that the FIFO buffer is full. Write requests are ignored when the FIFO is full if overflow protection option is enabled. In this case, initiating a write while full is not destructive to the FIFO. |
| almost_full_o | Output | Optional, almost full. When asserted, this signal indicates that only one more write can be performed before the FIFO is full. |
| prog_full_o | Output | Optional, programmable full. This signal is asserted when the number of words in the FIFO is greater than or equal to the assert threshold. It is deasserted when the number of words in the FIFO is less than the negate threshold. |
| wr_ack_o | Output | Optional, write acknowledge. This signal indicates that a write request (wr_en_i) during the prior clock cycle succeeded. |
| overflow_o | Output | Optional, overflow. This signal is exposed when:
Overflow Protection = Enable
This signal indicates that a write request
(wr_en_i) during the prior clock cycle was rejected because the FIFO
buffer is full. In this case, overflowing the FIFO is not
destructive to the contents of the
FIFO. Optional Signals = Enable
and Overflow Protection = Disable
This signal indicates that the previous write request
overflows the FIFO and it is destructive to the contents of the
FIFO. If this signal is asserted, it is required to reset the
FIFO. |
| Port | Direction | Description |
|---|---|---|
| rdata [m-1:0] | Output | Read data. The output data bus driven when reading the FIFO
buffer. m=DATA_WIDTH. |
| rd_en_i | Input | Read enable. If the FIFO buffer is not empty, asserting this signal causes data to be read from the FIFO (output on rdata). |
| empty_o | Output | Empty flag. When asserted, this signal indicates that the FIFO buffer is empty. When empty, Read requests are ignored if underflow protection option is enabled. In this case, initiating a read while empty is not destructive to the FIFO. |
| almost_empty_o | Output | Optional, almost empty flag. When asserted, this signal indicates that only one word remains in the FIFO buffer before it is empty. |
| prog_empty_o | Output | Optional, programmable empty. This signal is asserted when the number of words in the FIFO buffer is less than or equal to the assert threshold. It is de-asserted when the number of words in the FIFO exceeds the negate threshold. |
| rd_valid_o | Output | Optional, read valid. This signal indicates that valid data is available on the output bus (rdata). |
| underflow_o | Output | Optional, underflow. This signal is exposed when:
Underflow Protection =
Enable This signal indicates that a read
request (rd_en_i) during the prior clock cycle was rejected because
the FIFO buffer is empty. In this case, underflowing the FIFO is not
destructive to the FIFO. Optional Signals =
Enable and Underflow Protection =
Disable This signal indicates that the
previous read request underflows the FIFO and it is destructive to
the FIFO. If this signal is asserted, it is required to reset the
FIFO.
|