Synchronous FIFO Operation

The FIFO core signals are synchronized on the rising edge clock of the respective clock domain. If you want to synchronize to the falling clock edge, use an inverter before sending the signal to the clock input.

Standard Mode

The following waveform shows the FIFO behavior in standard mode when it is written until full and then read until empty. D1 and DN are the first and last data, respectively.

When overflow protection option is enabled, if the system tries to write data DN+1 when full_o is asserted, the core ignores DN+1 and asserts overflow_o. full_o deasserts during a read request, signaling that the FIFO is ready for more write requests. When the last data is read from the FIFO, the core asserts empty_o, indicating there is no more data. Further read requests when there is no more data triggers an assertion on underflow_o if the underflow protection option is enabled.

When overflow protection option is disabled, if the system tries to write data DN+1 when full_o is asserted, the core still writes DN+1. User logic needs to guarantee that it is not overflowing the FIFO by monitoring almost_full signal that indicates only 1 entry left before the FIFO is full. The same concept applies to underflow protection.

First-Word-Fall-Through Mode

First-Word-Fall-Through (FWFT), is a mode in which the first word written into the FIFO "falls through" and is available at the output without a read request. The following waveform shows the behavior of the FIFO in FWFT mode when it is written until full and then read until empty. D1 and DN are the first and last data, respectively.

The write behavior is the same as standard mode; the read behavior is different. When the first word is written into the FIFO buffer, the core deasserts empty_o and asserts rd_valid_o. There is one clock cycle of latency from wr_en_i to deassert empty_o and assert rd_valid_o. Hence, it is expected that the datacount_o is incremented 1 cycle earlier than the deassertation of the empty_o. Consequently, the first word that falls through the FIFO onto the rdata also has the one additional clock cycle of latency.

D1 is available on the rdata output data bus without a read request (that is, rd_en_i is not asserted). When the second data is written into the FIFO buffer, the output data does not change until there is a read request. When it detects a read request, the FIFO core outputs the next available data onto the output bus. If the current data is the last data DN and the core detects a read request, it asserts empty_o and deasserts rd_valid_o. Additional reads underflow the FIFO.