Features

  • 1 - 4 (user selectable) VexiiRiscv processor(s) with 7 pipeline stages (fetch, align-decompress, decode, issue, execute, memory, and writeback)
  • Interrupts and exception handling with machine and supervisor modes.
  • 20 - 400 MHz system clock frequency
  • 4 - 512 KB on-chip RAM with boot loader for SPI flash
  • Debug:
    • Supports standard RISC-V debug specification
    • Up to 4 hardware breakpoints
    • Up to 4 performance counters
    • Supports co-debug with the FPGA debugger
  • Memory controller for DDR3, LPDDR4x, or HyperRAM memories, supports memory module sizes from 4 MB to 8 GB:
    • User-configurable external memory bus frequency:
      • 1 half-duplex AXI3 interface (up to 512 bits) or 1 full-duplex AXI4 interface (up to 512 bits) to communicate with the external memory
      • 400 MHz DDR3 clock frequency, 800 Mbps
      • 1,600 MHz LPDDR4x clock frequency, 3,200 Mbps
      • 250 MHz HyperRAM clock frequency, 500 Mbps
  • Up to 2 AXI slave channels for user logic, data widths from 32 to 512-bits, with memory coherency
  • 1 AXI master channel to user logic
  • Includes a multi-way L1 instruction and data cache
  • Includes an optional L2 cache
  • Includes an optional branch predictor
  • Includes an optional physical memory protection unit
  • Includes an optional hardware and software pre-fetcher
  • Includes a floating-point unit (FPU)
  • Includes an optional Linux memory management unit (SV39 MMU)
  • Includes an optional custom instruction interface with 1,024 IDs to perform various functions
  • Supports optional RISC-V extensions such as single and double-digit floating point, atomic, compressed, bit manipulation, and cache block management.
  • I/O peripherals:
    • Up to 32 GPIOs
    • Up to 5 I2C masters
    • Clint timer
    • Platform-level interrupt controller (PLIC)
    • Watchdog timer
    • Up to 3 SPI masters
    • Up to 3 user timers
    • Up to 3 UARTs with 115,200 baud rates
    • Up to 5 slave user peripherals with APB3 interface
    • Up to 8 user interrupts

FPGA Support

The Sapphire RV64 SoC supports all Trion FPGAs (except for T4 and T8) and all Titanium FPGAs. However, you may only be able to use some of the features in certain devices. For example, the DDR controller only works with FPGAs that have a hardened DDR controller block.

Resource Utilization and Performance

The Sapphire RV64 SoC is configurable. These tables show the resource usage for various configurations.

Basic L2:
  • Single-core RV64, with 64 KB L2 cache and 1-way 4 KB data and instruction cache.
  • RV64 I, M, A, and C extensions enabled.
  • 256-bit width AXI4 for external memory, 1 SPI, and 1 UART.
Basic L1:
  • Same configurations as Basic L2, but excluding the L2 cache.
Advanced L2:
  • Single-core RV64, with 64 KB L2 cache, 1-way 4 KB data, and instruction cache.
  • All available extensions enabled, except for Zicbom.
  • All extended features enabled.
  • 256-bit width AXI4 for external memory, 1 SPI, and 1 UART.
Advanced L1:
  • Same configuration as Advanced L2, but excluding the L2 cache.
Table 1. Titanium Ti375 C529 Resource Utilization and Performance
Configuration Logic/Adders Flip Flops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Basic L2 14,258 12,624 188 17 278 2026.1
Basic L1 10,740 9,024 91 17 271
Advanced L2 27,250 17,869 225 17 252
Advanced L1 23,838 14,253 128 17 250
Table 2. Topaz Tz170 J484 Resource Utilization and Performance
Configuration Logic/Adders Flip Flops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Basic L2 14,258 12,624 188 17 170 2026.1
Basic L1 10,740 9,024 91 17 176
Advanced L2 27,250 17,869 225 17 167
Advanced L1 23,838 14,253 128 17 164

Table 3. Trion T120 F324 Resource Utilization and Performance
Configuration Logic/Adders Flip Flops Memory Blocks DSP48 Blocks fMAX (MHz) Efinity Version
Basic L2 14,309 12,468 259 17 77 2026.1
Basic L1 10,741 9,046 98 17 77
Advanced L2 26,894 17,903 303 17 65
Advanced L1 23,612 14,355 142 17 65

Performance Benchmark

The performance of the CPU can be benchmarked with Dhrystone and Coremark benchmark programs for easier comparison between processors. While theSapphire RV64 SoC uses the same VexiiRiscv core, the configurations such as memory, cache, and additional extensions would affect the performance of the system. The Dhrystone and Coremark scores for each of the configurations are tabulated in the table based on Titanium Ti375 C529 Development Board.

Development board:

Efinity version 2026.1

Table 4. Performance Benchmark
Configuration Coremark (MHz) Dhrystone (MHz)
Basic L2 1.25 1.17
Basic L1 1.23 1.17
Advanced L2 1.57 1.54
Advanced L1 1.56 1.37