Functional Description

The Sapphire RV64 SoC incorporates 1 to 4 64-bit RISC-V processors that have an instruction cache and data cache with up to 8-ways (4 KB per way), each way is equipped with 4 KB, 64 KB to 512 KB 8-ways L2 cache, 4 - 512 KB of on-chip RAM, and a variety of peripherals (including 1 - 5 APB3 slave peripherals and 2 AXI slaves and 1 AXI master). You can configure the operating frequency from 20 to 400 MHz (the design's fMAX limits the actual performance).

Other optional CPU micro-architectures, such as floating-point unit (FPU), a dynamic branch predictor, software and hardware prefetchers, custom instruction interfaces, physical memory protection, and an SV39 memory management unit (MMU), can be configured with the IP Manager.

The SoC includes a CLINT timer, a platform local interrupt controller, a watchdog timer, 1 - 5 I2C peripherals, 1 - 3 UARTs, 1 - 3 user timers, 1 - 8 user interrupts, and 1 - 3 SPI masters. The default configuration supports a half-duplex and a full-duplex (address channel only) AXI bus with up to 512 bits to communicate with the Efinix LPDDR4x controller or HyperRAM controller.
  • DDR controller—This core uses the Trion or Titanium FPGAs hard DDR DRAM interface to reset an external DRAM module (resets and reinitializes the Trion or Titanium FPGA's DDR interface, which includes the DDR module(s)).
  • HyperRAM controller—This core controls HyperRAM memory modules. You can customize the SoC using the IP Manager in the Efinity® software.

Figure 1. Sapphire RV64 Block Diagram