Floating-Point Unit
The Sapphire RV64 floating-point unit (FPU) is an optional, pipeline-integrated hardware unit that implements RISC-V floating-point instructions (single and optionally double-precision). It operates alongside the integer pipeline but uses a separate floating-point register file (f0–f31).
When a floating-point instruction is decoded, it is dispatched to the FPU, where operands are read from the FP registers. The FPU first unpacks the operands into sign, exponent, and mantissa. Concurrently, it also checks for special values such as Not-a-Number (NaN), infinity, subnormal, or zero.
- Addition or subtraction aligns exponents and adds mantissas.
- Multiplication multiplies mantissas and adjusts exponents.
- Division or square-root uses an iterative algorithm (higher latency).
- Fused multiply-add performs combined operations efficiently.
After computation, the result is normalized and rounded according to the selected rounding mode. Any floating-point exceptions (e.g., overflow, divide-by-zero, etc.) are recorded in the FCSR register.
Finally, the result is packed back into IEEE-754 format and written to the FP register file. The FPU is pipelined, allowing multiple operations in flight, but may stall on dependencies or on long-latency operations such as division. It is also configurable, meaning it can be enabled or disabled, and tailored to different precision levels depending on system requirements.