AXI Interface

The Sapphire RV64 has a 512-bit half duplex AXI3 interface or up to a 512-bit full duplex AXI4 interface to communicate to external memory. You configure it on the Memory tab in the IP Configuration wizard. Additionally it has two optional full duplex AXI4 interfaces to connect to user logic. You configure it on the AXI4 tab in the IP Configuration wizard.

  • There is one AXI4 master interface (axiA), which is compatible with AXI-Lite (axlen is always 0).
  • There is one AXI4 master interface (axiB), which is routed through cache region and able to do read or write burst transfer.
  • There are two optional full duplex AXI4 slave interfaces. You can configure the width as 32, 64, 128, 256, or 512-bit.
Notice: Refer to the AMBA AXI and ACE Protocol Specification for AXI channel descriptions and handshake information.

AXI Interface to External Memory

Table 1. Full-Duplex Address Channel for Read and Write
Port Direction Description
io_ddrA_aw_valid Output External memory write address valid.
io_ddrA_aw_ready Input External memory write address ready.
io_ddrA_aw_payload_addr[m:0] Output External memory write address. m is configurable up to 33 bits wide.
io_ddrA_aw_payload_id[n:0] Output External memory write address ID. n is configurable either 6 or 8 bits wide.
io_ddrA_aw_payload_region[3:0] Output External memory write region identifier.
io_ddrA_aw_payload_len[7:0] Output External memory write burst length.
io_ddrA_aw_payload_size[2:0] Output External memory write burst size.
io_ddrA_aw_payload_burst[1:0] Output External memory write burst type, INCR only.
io_ddrA_aw_payload_lock Output External memory write lock type.
io_ddrA_aw_payload_cache[3:0] Output External memory write memory type.
io_ddrA_aw_payload_qos[3:0] Output External memory write quality of service.
io_ddrA_aw_payload_prot[2:0] Output External memory write protection type.
io_ddrA_aw_payload_allStrb Output External memory write all strobe.
io_ddrA_ar_valid Output External memory read address valid.
io_ddrA_ar_ready Input External memory read address ready.
io_ddrA_ar_payload_addr[m:0] Output External memory read address. m is configurable up to 33 bits wide.
io_ddrA_ar_payload_id[n:0] Output External memory read address ID. n is configurable either 6 or 8 bits wide.
io_ddrA_ar_payload_region[3:0] Output External memory read region identifier.
io_ddrA_ar_payload_len[7:0] Output External memory burst length.
io_ddrA_ar_payload_size[2:0] Output External memory read burst size.
io_ddrA_ar_payload_burst[1:0] Output External memory read burst type, INCR only.
io_ddrA_ar_payload_lock Output External memory read lock type.
io_ddrA_ar_payload_cache[3:0] Output External memory read memory type.
io_ddrA_ar_payload_qos[3:0] Output External memory read quality of service.
io_ddrA_ar_payload_prot[2:0] Output External memory read protection type.
Table 2. Half-Duplex Address Channel for Read and Write
Port Direction Description
io_ddrA_arw_valid Output External memory address valid.
io_ddrA_arw_ready Input External memory address ready.
io_ddrA_arw_payload_addr[m:0] Output External memory address. m is configurable up to 33 bits wide.
io_ddrA_arw_payload_id[n:0] Output External memory address ID. n is configurable either 6 or 8 bits wide.
io_ddrA_arw_payload_region[3:0] Output External memory region identifier.
io_ddrA_arw_payload_len[7:0] Output External memory burst length.
io_ddrA_arw_payload_size[2:0] Output External memory burst size.
io_ddrA_arw_payload_burst[1:0] Output External memory burst type, INCR only.
io_ddrA_arw_payload_lock Output External memory lock type.
io_ddrA_arw_payload_cache[3:0] Output External memory memory type.
io_ddrA_arw_payload_qos[3:0] Output External memory quality of service.
io_ddrA_arw_payload_prot[2:0] Output External memory protection type.
io_ddrA_arw_payload_write Output External memory address read or write selection: 0: Read
1: Write
Table 3. Write Data Channel
Port Direction Description
io_ddrA_w_valid Output External memory write valid.
io_ddrA_w_ready Input External memory write ready.
io_ddrA_w_payload_data[n:0] Output External memory write data.
n is configurable up to 512 bits wide.
io_ddrA_w_payload_strb[m:0] Output External memory write strobe.
m is the width of io_ddrA_w_payload_data[n:0] divided by 8.
io_ddrA_w_payload_last Output External memory write last.

Table 4. Write Respond Channel
Port Direction Description
io_ddrA_b_valid Input External memory write respond valid.
io_ddrA_b_ready Output External memory respond ready.
io_ddrA_b_payload_id[n:0] Input External memory respond ID. n is configurable either 6 or 8 bits wide.
io_ddrA_b_payload_resp[1:0] Input External memory write respond.
Table 5. Read Data Channel
Port Direction Description
io_ddrA_r_valid Input External memory read valid.
io_ddrA_r_ready Output External memory read ready.
io_ddrA_r_payload_data[m:0] Input External memory read data.
m is user configurable up to 512 bits wide.
io_ddrA_r_payload_id[n:0] Input External memory read ID. n is configurable either 6 or 8 bits wide.
io_ddrA_r_payload_resp[1:0] Input External memory read respond.
io_ddrA_r_payload_last Input External memory read last.

AXI Master A (axiA) AXI4 Interface

Table 6. Write Address Channel
Port Direction Description
axiA_awvalid Output AXI master A write address valid.
axiA_awready Input AXI master A write address ready.
axiA_awaddr[31:0] Output AXI master A write address.
axiA_awid[7:0] Output AXI master A write address ID.
axiA_awregion[3:0] Output AXI master A region identifier.
axiA_awlen[7:0]1 Output AXI master A burst length.
axiA_awsize[2:0] Output AXI master A burst size.
axiA_awburst[1:0] Output AXI master A burst type, INCR only.
axiA_awlock Output AXI master A lock type.
axiA_awcache[3:0] Output AXI master A memory type.
axiA_awqos[3:0] Output AXI master A quality of service.
axiA_awprot[2:0] Output AXI master A protection type.

Table 7. Write Data Channel
Port Direction Description
axiA_wvalid Output AXI master A write valid.
axiA_wready Input AXI master A write ready.
axiA_wdata[31:0] Output AXI master A write data.
axiA_wstrb[3:0] Output AXI master A write strobe.
axiA_wlast Output AXI master A write last.
Table 8. Write Respond Channel
Port Direction Description
axiA_bvalid Input AXI master A write respond valid.
axiA_bready Output AXI master A respond ready.
axiA_bid[7:0] Input AXI master A respond ID.
axiA_bresp[1:0] Input AXI master A write respond.
Table 9. Read Address Channel
Port Direction Description
axiA_arvalid Output AXI master A read address valid.
axiA_arready Input AXI master A read address ready.
axiA_araddr[31:0] Output AXI master A read address.
axiA_arid[7:0] Output AXI master A read address ID.
axiA_arregion[3:0] Output AXI master A region identifier.
axiA_arlen[7:0]2 Output AXI master A burst length.
axiA_arsize[2:0] Output AXI master A burst size.
axiA_arburst[1:0] Output AXI master A burst type, INCR only.
axiA_arlock Output AXI master A lock type.
axiA_arcache[3:0] Output AXI master A memory type.
axiA_arqos[3:0] Output AXI master A quality of service.
axiA_arprot[2:0] Output AXI master A protection type.
Table 10. Read Data Channel
Port Direction Description
axiA_rvalid Input AXI master A read valid.
axiA_rready Output AXI master A read ready.
axiA_rdata[31:0] Input AXI master A read data.
axiA_rid[7:0] Input AXI master A read ID.
axiA_rresp[1:0] Input AXI master A read respond.
axiA_rlast Input AXI master A read last.

AXI Master B (axiB) AXI4 Interface

Table 11. Clock and Reset
Port Direction Description
axiB_clk Input AXI master B clock.
axiB_reset Output AXI master B active high reset.
Table 12. Address Channel for Read and Write
Port Direction Description
axiB_aw_valid Output AXI master B write address valid.
axiB_aw_ready Input AXI master B write address ready.
axiB_aw_payload_addr[m:0] Output AXI master B write address. m is configurable up to 37 bits wide.
axiB_aw_payload_id[7:0] Output AXI master B write address ID.
axiB_aw_payload_region[3:0] Output AXI master B write region identifier.
axiB_aw_payload_len[7:0] Output AXI master B write burst length.
axiB_aw_payload_size[2:0] Output AXI master B write burst size.
axiB_aw_payload_burst[1:0] Output AXI master B write burst type.
axiB_aw_payload_lock Output AXI master B write lock type.
axiB_aw_payload_cache[3:0] Output AXI master B write memory type.
axiB_aw_payload_qos[3:0] Output AXI master B write quality of service.
axiB_aw_payload_prot[2:0] Output AXI master B write protection type.
axiB_aw_payload_allstrb Output AXI master B write all strobe.
axiB_ar_valid Output AXI master B read address valid.
axiB_ar_ready Input AXI master B read address ready.
axiB_ar_payload_addr[m:0] Output External memory read address. m is configurable up to 37 bits wide.
axiB_ar_payload_id[5:0] Output AXI master B read address ID.
axiB_ar_payload_region[3:0] Output AXI master B read region identifier.
axiB_ar_payload_len[7:0] Output AXI master B burst length.
axiB_ar_payload_size[2:0] Output AXI master B read burst size.
axiB_ar_payload_burst[1:0] Output AXI master B read burst type, INCR only.
axiB_ar_payload_lock Output AXI master B read lock type.
axiB_ar_payload_cache[3:0] Output AXI master B read memory type.
axiB_ar_payload_qos[3:0] Output AXI master B read quality of service.
axiB_ar_payload_prot[2:0] Output AXI master B read protection type.

Table 13. Write Data Channel
Port Direction Description
axiB_w_valid Output AXI master B write valid.
axiB_w_ready Input AXI master B write ready.
axiB_w_payload_data[n:0] Output AXI master B write data. n is user configurable up to 512 bits wide.
axiB_w_payload_strb[m:0] Output AXI master B write strobe. m is the width of axiB_w_payload_data[n:0] divided by 8.
axiB_w_payload_last Output AXI master B write last.
Table 14. Write Respond Channel
Port Direction Description
axiB_b_valid Input AXI master B write respond valid.
axiB_b_ready Output AXI master B respond ready.
axiB_b_payload_id[7:0] Input AXI master B respond ID.
axiB_b_payload_resp[1:0] Input AXI master B write respond.

Table 15. Read Data Channel
Port Direction Description
axiB_r_valid Input AXI master B read valid.
axiB_r_ready Output AXI master B read ready.
axiB_r_payload_data[m:0] Input AXI master B read data. m is user configurable up to 512 bits wide.
axiB_r_payload_id[7:0] Input AXI master B read ID.
axiB_r_payload_resp[1:0] Input AXI master B read respond.
axiB_r_payload_last Input AXI master B read last.

AXI Slave AXI4 Interface

Table 16. Write Address ChannelWhere n is the channel number.
Port Direction Description
io_ddrMasters_n_aw_valid Input AXI slave write address valid.
io_ddrMasters_n_aw_ready Output AXI slave write address ready.
io_ddrMasters_n_aw_payload_addr[m:0] Input AXI slave write address. m is configurable up to 37 bits wide.
io_ddrMasters_n_aw_payload_id[3:0] Input AXI slave write address ID.
io_ddrMasters_n_aw_payload_region[3:0] Input AXI slave region identifier.
io_ddrMasters_n_aw_payload_len[7:0] Input AXI slave burst length.
io_ddrMasters_n_aw_payload_size[2:0] Input AXI slave burst size.
io_ddrMasters_n_aw_payload_burst[1:0] Input AXI slave burst type.
io_ddrMasters_n_aw_payload_lock Input AXI slave lock type.
io_ddrMasters_n_aw_payload_cache[3:0] Input AXI slave memory type.
io_ddrMasters_n_aw_payload_qos[3:0] Input AXI slave quality of service.
io_ddrMasters_n_aw_payload_prot[2:0] Input AXI slave protection type.
Table 17. Write Data ChannelWhere n is the channel number.
Port Direction Description
io_ddrMasters_n_w_valid Input AXI slave write valid.
io_ddrMasters_n_w_ready Output AXI slave write ready.
io_ddrMasters_n_w_payload_data[m:0] Input AXI slave write data.
m is 31, 63, 127, 255, or 511.
io_ddrMasters_n_w_payload_strb[p:0] Input AXI slave write strobe. p is the width of io_ddrMasters_n_w_payload_data [m:0] divided by 8.
io_ddrMasters_n_w_payload_last Input AXI slave write last.
Table 18. Write Respond ChannelWhere n is the channel number.
Port Direction Description
io_ddrMasters_n_b_valid Output AXI slave write respond valid.
io_ddrMasters_n_b_ready Input AXI slave respond ready.
io_ddrMasters_n_b_payload_id[7:0] Output AXI slave respond ID.
io_ddrMasters_n_b_payload_resp[1:0] Output AXI slave write respond.

Table 19. Read Address ChannelWhere n is the channel number.
Port Direction Description
io_ddrMasters_n_ar_valid Input AXI slave read address valid.
io_ddrMasters_n_ar_ready Output AXI slave read address ready.
io_ddrMasters_n_ar_payload_addr[m:0] Input AXI slave read address.
m is configurable up to 37 bits wide.
io_ddrMasters_n_ar_payload_id[3:0] Input AXI slave read address ID.
io_ddrMasters_n_ar_payload_region[3:0] Input AXI slave region identifier.
io_ddrMasters_n_ar_payload_len[7:0] Input AXI slave burst length.
io_ddrMasters_n_ar_payload_size[2:0] Input AXI slave burst size.
io_ddrMasters_n_ar_payload_burst[1:0] Input AXI slave burst type.
io_ddrMasters_n_ar_payload_lock Input AXI slave lock type.
io_ddrMasters_n_ar_payload_cache[3:0] Input AXI slave memory type.
io_ddrMasters_n_ar_payload_qos[3:0] Input AXI slave quality of service.
io_ddrMasters_n_ar_payload_prot[2:0] Input AXI slave protection type.
Table 20. Read Data ChannelWhere n is the channel number.
Port Direction Description
io_ddrMasters_n_r_valid Output AXI slave read valid.
io_ddrMasters_n_r_ready Input AXI slave read ready.
io_ddrMasters_n_r_payload_data[m:0] Output External memory read data.
m is 31, 63, 127, 255 or 511.
io_ddrMasters_n_r_payload_id[7:0] Output AXI slave memory read ID.
io_ddrMasters_n_r_payload_resp[1:0] Output AXI slave memory read respond.
io_ddrMasters_n_r_payload_last Output AXI slave memory read last.
1 axiA_awlen always outputs 0, that is, a burst length of 1. This setting makes the axiA channel compatible with AXI-Lite.
2 axiA_arlen always outputs 0, that is, a burst length of 1. This setting makes the axiA channel compatible with AXI-Lite.