SV39 Memory Management Unit

The SV39 Memory Management Unit (MMU) is used in RISC-V systems to support virtual memory for 64-bit processors with 39-bit virtual addresses. Its primary role is to translate virtual addresses used by software into physical addresses used by the memory system, while also enforcing access permissions and page-level protection. SV39 supports virtual addresses up to 512 GB in size, organized into three hierarchical levels of page tables filled with pages of 1 GB 2 MB, or 4 KB. The virtual address is divided into three virtual page number (VPN) fields and a page offset. Each VPN field is 9 bits wide, corresponding to indices used during page table traversal, while the 12-bit offset selects a byte within a 4 KB page.

SV39 employs a three-level page table hierarchy to perform address translation. The base of this hierarchy is pointed to by the supervisor's address translation and protection (satp) register, which holds the physical page number of the root page table, along with control information such as the address space identifier (ASID) and the mode field that enables SV39. During translation, the hardware navigates the page tables by first indexing the root table using VPN[2], followed by the pointer pointing to the next level table and indexing with VPN[1], and finally repeating the process with VPN[0] at the lowest level. Each page table contains 512 entries, and each entry is a page table entry (PTE) that is 64 bits wide.

The Sapphire RV64 includes a translation lookaside buffer (TLB), which caches recent virtual-to-physical translations. Once a TLB hit, the translation completes quickly without accessing memory. For a miss, a hardware page table walker performs the multi-level lookup described earlier, which may require up to three memory accesses before the final data access even begins. Due to this reason, maintaining a high TLB hit rate is critical for performance. When the page tables are modified by software, the TLB must be explicitly synchronized using instructions such as SFENCE.VMA to ensure stale translations are not used.

The PTE itself contains several control and status bits. This includes a valid bit to indicate whether the entry is usable, and permission bits for read, write, and execute access. If a failure arises during translation, such as encountering an invalid entry, insufficient permissions, or a malformed superpage, the MMU raises a page fault exception, which is then handled by the operating system.