Pipeline Stages

Stage 1—Instruction fetch
  • PC calculation
  • Branch prediction (if enabled)
  • Next PC selection
  • Instruction memory access (I-cache or bus)
  • Branch prediction fetch
Stage 2—Pre-decode or Align
  • Instruction word fetched
  • Instruction alignment (important for compressed instructions)
  • Basic decoding preparation
  • Apply branch prediction
Stage 3—Decode
  • Full instruction decodes
  • Hold instruction with pending dependencies
Stage 4—Issue or Register read
  • Register file read
  • Bypass results of inflight instruction
  • Immediate generation
Stage 5—Execute
  • ALU operations
  • Branch calculation
  • Address calculation for load or store
Stage 6—Memory access
  • Data cache access
  • Branch operations
Stage 7—Writeback
  • Data cache response
  • Load or store completion
  • I/O bus accesses
  • Write results back to register file
  • Final commit stage (for in-order core)