Clock

Table 1. Clock Ports

Port	Direction	Description
io_systemClock	Input	Provides a 20 - 400 MHz clock for the SoC.
io_peripheralClock	Input	Provides a 20 - 200 MHz clock for the APB3 peripherals and AXI4 master A.
io_memoryClock	Input	Provides a clock for the external memory bus. The frequency used is user-defined.
io_ddrMasters_0_clk	Input	Provides a clock for AXI4 slave 0.
io_ddrMasters_1_clk	Input	Provides a clock for AXI4 slave 1.
axiB_clk	Input	Provides a clock for AXI4 master B.