Memory Coherency with DMA

The Sapphire RV64 SoC has a configuration in which the CPU always sees the correct data by utilizing L2 as the central coherency point. There is no requirement for software flushing for L1 or L2 cache.

Role of L2 in Coherency

The L2 cache acts as a central coherence point (directory):
  • Tracks which cores hold which cache lines
  • Coordinates:
    • Invalidations
    • Data forwarding
    • Writebacks
  • Reduces unnecessary memory accesses by serving as an intermediary
    • On DMA Read:
      • If data is 'dirty' in L1:
        • L2 forces L1 writeback into L2
        • Supplies the latest data to DMA
    • On DMA Write:
      • L2
        • Flush L1 shared or exclusive copies
        • Invalidates L1 copies