L2 Cache

The L2 cache in the Sapphire RV64 SoC is a shared, higher-level cache that sits between the CPU cores (with their private L1 caches) and the main memory (e.g., DDR). Its main purpose is to reduce memory latency and external memory traffic by storing recently accessed data that is shared across cores or reused frequently, and implementing memory coherency between the CPU and DMA through dictionary lookup.

In the Sapphire RV64 SoC setup, each core has its own L1 instruction and data caches, while the L2 cache is unified and shared. When a core performs a memory access, it first checks its L1 cache. If the data is not found (L1 miss), the request is forwarded to the L2 cache. If the L2 cache also misses, the request goes to the main memory. When data is fetched from memory, it is usually filled into both L2 and L1, improving future access speed.

The L2 cache in Sapphire RV64 SoC uses a write-back policy, meaning that modified data ('dirty' lines) are written back to main memory only when they are evicted from the cache, rather than on every write. This improves performance by reducing memory bandwidth usage.