Important Notes

Machine Status Register (mstatus): 0x300

The availability of implemented CSRs depends on the enablement of the following SoC features.
  • XS[1:0]—Custom instruction
  • FS[1:0]—Floating point
  • SIE, SPIE, SPP, TVM, TSR, SXL, MXR, SUM—Supervisor mode
Figure 1. Data Mapping of the Machine Status Register (mstatus)

Machine Exception Delegation (medeleg): 0x302

Not all exception delegations are implemented. Below is the list of exceptions supported:
Code Exception
0 Instruction address misaligned.
3 Breakpoint
8 Ecall from U-mode
9 Ecall from S-mode
12 Instruction page fault
13 Load page fault
15 Store / AMO page fault

Machine Interrupt Delegation (mideleg): 0x303

Not all exception delegations are implemented. Below is the list of interrupts supported:

Code Interrupt
1 Supervisor software interrupt
5 Supervisor timer interrupt
9 Supervisor external interrupt

Machine Trap-Vector Base-Address Register (mtvec): 0x305

MTVEC supports direct mode interrupt only. Vectored mode is not supported.

Supervisor Trap-Vector (stvec): 0x105

STVEC supports direct mode interrupt only. Vectored mode is not supported.

0x7FF Custom CSR for Hardware Data Prefetch

This custom CSR is available in Sapphire RV64 SoC only.