Memory Coherency

When multiple cores are present, each core may have their own L1 data cache. This introduces the problem of memory coherency, where all cores see a consistent view of memory.

The Sapphire RV64 SoC maintains coherency using a cache-coherence protocol (typically MESI-like, depending on configuration). The idea is:
  • Each cache line is tracked with a state such as:
    • Modified (M): data is updated and only exists in this cache
    • Exclusive (E): clean copy, only in one cache
    • Shared (S): clean copy, possibly in multiple caches
    • Invalid (I): not valid