Address Map

Efinix recommends that you always refer to the parameter name when referencing an address in firmware because the address range is updated according to different configuration, not by the actual address. The parameter names and address mappings are defined in /embedded_sw/<module>/bsp/ efinix/EfxSapphireSocRV64/include/soc.h.

Note: If you need to update the address map, use the IP Configuration wizard to change the addressing and then regenerate the SoC. This method keeps the software soc.h and FPGA netlist definitions aligned.

Table 1. Default Address Map, Interrupt ID, and Cached Channels
Device	Address	Size	Interrupt ID	Region
Reserved	0x00_0000_0000	16 MB	–	–
On-Chip RAM	0x00_0100_0000	512 KB	–	Cache
Reserved	0x00_0108_0000	15 MB + 512 KB	–	–
CLINT	0x00_0200_0000	64 KB	–	I/O
Reserved	0x00_0201_0000	3 MB + 960 KB	–	–
PLIC	0x00_0240_0000	4 MB	–	I/O
Reserved	0x00_0280_0000	4 MB	–	–
L2 Cache Control	0x00_02C0_0000	4 KB	31	I/O
Reserved	0x00_02C0_1000	3 MB + 1020 KB	–	–
Watchdog Timer	0x00_0300_0000	4 KB	26,27	I/O
Reserved	0x00_0300_1000	15 MB + 1020 KB	–	–
Reserved	0x00_0400_0000	64 MB	–	–
User Timer 0	0x00_0800_0000	64 KB	20	I/O
User Timer 1	0x00_0801_0000	64 KB	21	I/O
User Timer 2	0x00_0802_0000	64 KB	22	I/O
UART 0	0x00_0803_0000	64 KB	1	I/O
UART 1	0x00_0804_0000	64 KB	2	I/O
UART 2	0x00_0805_0000	64 KB	3	I/O
SPI 0	0x00_0806_0000	64 KB	6	I/O
SPI 1	0x00_0807_0000	64 KB	7	I/O
SPI 2	0x00_0808_0000	64 KB	8	I/O

Table 2. Default Address Map, Interrupt ID, and Cached Channels (Continue)
Device	Address	Size	Interrupt ID	Region
I2C 0	0x00_0809_0000	64 KB	11	I/O
I2C 1	0x00_080A_0000	64 KB	12	I/O
I2C 2	0x00_080B_0000	64 KB	13	I/O
I2C 3	0x00_080C_0000	64 KB	14	I/O
I2C 4	0x00_080D_0000	64 KB	15	I/O
GPIO 0	0x00_080E_0000	64 KB	16,17	I/O
GPIO 1	0x00_080F_0000	64 KB	18,19	I/O
Reserved	0x00_0810_0000	15 MB	–	–
APB 0	0x00_0900_0000	16 MB	–	–
APB 1	0x00_0A00_0000	16 MB	–	–
APB 2	0x00_0B00_0000	16 MB	–	–
APB 3	0x00_0C00_0000	16 MB	–	–
APB 4	0x00_0D00_0000	16 MB	–	–
Reserved	0x00_0E00_0000	32 MB	–	–
AXI A	0x00_1000_0000	256 MB	30	I/O
Reserved	0x00_2000_0000	31 GB + 512 MB	–	–
DDR	0x08_0000_0000	8 GB	–	Cache
Reserved	0x0A_0000_0000	24 GB	–	–
AXI B	0x10_0000_0000	64 GB	–	Cache
External interrupt	-	-	32-39	–

When accessing the addresses in the I/O region, type cast the pointer with the keyword volatile. The compiler recognizes this as a memory-mapped I/O register without optimizing the read/write access. The following command shows an example of the casting:

*((volatile u32*) address);

For the cached regions, the burst length is equivalent to an AXI burst length of 8. For the I/O region, the burst length is equivalent to an AXI burst length of 1. The AXI user master is compatible with AXI-Lite by disconnecting unused outputs and driving a constant 1 to the input port.

Note: The RISC-V GCC compiler does not support user address spaces starting at 0x0000_0000.