Features

  • 4 VexRiscv processor(s) with 6 pipeline stages (fetch, injector, decode, execute, memory, and write back), interrupts, and exception handling with machine mode and supervisor mode.
  • Up to 1 GHz system clock frequency
  • 16 KB on-chip RAM with boot loader for SPI flash
  • Memory controller for LPDDR4x
    • Supports memory module sizes of 3.7 GB
    • 1 full-duplex 512-bits AXI4 interface to communicate with the external memory
    • User-configurable external memory bus frequency
  • 1 AXI slave channel for user logic, data width of 128-bits
  • 1 AXI master channel to user logic
  • Each core includes:
    • 4-way 16 KB data and instruction caches
    • Floating point unit (FPU)
    • Linux memory management unit (MMU)
    • Custom instruction interface with 1,024 IDs to perform various functions
  • Supports RISC-V extensions such as integer, multiply, atomic, compressed, single, and double-digit floating point.
  • JTAG debug module with 8 hardware breakpoints
  • Peripherals:
    • 2 user timers
    • 24 user interrupts

FPGA Support

The Sapphire High-Performance RISC-V SoC uses the hardened RISC-V block in the following devices and only supports these FPGAs:

Table 1. Sapphire High-Performance RISC-V SoC Device Support
FPGA Family Supported Device
Titanium Ti85, Ti135, Ti165, Ti240, and Ti375
Topaz Tz75, Tz100, Tz200, Tz325

Performance Benchmark

The performance of the CPU can be benchmarked with Dhrystone and Coremark benchmark programs for easier comparison between processors.

Development board: Titanium

Efinity version 2025.2

Table 2. Performance Benchmark
GCC Option Coremark (/MHz) Dhrystone (/MHz)
GCC8.3.0 2.35 1.24