AXI Interface

The Sapphire high-performance RISC-V SoC has a 512-bit full duplex AXI4 interface to communicate to external memory.

Additionally it has a full duplex AXI4 interface to connect to user logic.
  • There is one AXI4 master interface, which is compatible with AXI-Lite (axlen is always 0).
  • There is one optional full duplex AXI4 slave interfaces with 128-bit data width.
Notice: Refer to the AMBA AXI and ACE Protocol Specification for AXI channel descriptions and handshake information.

AXI Interface to External Memory

Table 1. AXI Master Full-Duplex Address Channel for Read and Write
Port Direction Description
io_ddrA_aw_valid Output External memory write address valid.
io_ddrA_aw_ready Input External memory write address ready.
io_ddrA_aw_payload_addr[31:0] Output External memory write address.
io_ddrA_aw_payload_id[7:0] Output External memory write address ID.
io_ddrA_aw_payload_region[3:0] Output External memory write region identifier.
io_ddrA_aw_payload_len[7:0] Output External memory write burst length.
io_ddrA_aw_payload_size[2:0] Output External memory write burst size.
io_ddrA_aw_payload_burst[1:0] Output External memory write burst type, INCR only.
io_ddrA_aw_payload_lock Output External memory write lock type.
io_ddrA_aw_payload_cache[3:0] Output External memory write memory type.
io_ddrA_aw_payload_qos[3:0] Output External memory write quality of service.
io_ddrA_aw_payload_prot[2:0] Output External memory write protection type.
io_ddrA_aw_payload_allStrb Output External memory write all strobe.
io_ddrA_ar_valid Output External memory read address valid.
io_ddrA_ar_ready Input External memory read address ready.
io_ddrA_ar_payload_addr[31:0] Output External memory read address.
io_ddrA_ar_payload_id[7:0] Output External memory read address ID.
io_ddrA_ar_payload_region[3:0] Output External memory read region identifier.
io_ddrA_ar_payload_len[7:0] Output External memory burst length.
io_ddrA_ar_payload_size[2:0] Output External memory read burst size.
io_ddrA_ar_payload_burst[1:0] Output External memory read burst type, INCR only.
io_ddrA_ar_payload_lock Output External memory read lock type.
io_ddrA_ar_payload_cache[3:0] Output External memory read memory type.
io_ddrA_ar_payload_qos[3:0] Output External memory read quality of service.
io_ddrA_ar_payload_prot[2:0] Output External memory read protection type.

Table 2. AXI Master Write Data Channel
Port Direction Description
io_ddrA_w_valid Output External memory write valid.
io_ddrA_w_ready Input External memory write ready.
io_ddrA_w_payload_data[n:0] Output External memory write data.
The length is fixed at 512-bit.
io_ddrA_w_payload_strb[m:0] Output External memory write strobe.
m is the width of io_ddrA_w_payload_data[n:0] divided by 8.
The length is fixed at 64-bit.
io_ddrA_w_payload_last Output External memory write last.
Table 3. AXI Master Write Respond Channel
Port Direction Description
io_ddrA_b_valid Input External memory write respond valid.
io_ddrA_b_ready Output External memory respond ready.
io_ddrA_b_payload_id[7:0] Input External memory respond ID.
io_ddrA_b_payload_resp[1:0] Input External memory write respond.
Table 4. AXI Master Read Data Channel
Port Direction Description
io_ddrA_r_valid Input External memory read valid.
io_ddrA_r_ready Output External memory read ready.
io_ddrA_r_payload_data[n:0] Input External memory read data.
The length is fixed at 512-bit.
io_ddrA_r_payload_id[7:0] Input External memory read ID.
io_ddrA_r_payload_resp[1:0] Input External memory read respond.
io_ddrA_r_payload_last Input External memory read last.

AXI Interface to User Logic

Table 5. User Master Write Address Channel
Port Direction Description
axiA_awvalid Output User write address valid.
axiA_awready Input User write address ready.
axiA_awaddr[31:0] Output User write address.
axiA_awid[7:0] Output User write address ID.
axiA_awregion[3:0] Output User region identifier.
axiA_awlen[7:0]1 Output User burst length.
axiA_awsize[2:0] Output User burst size.
axiA_awburst[1:0] Output User burst type, INCR only.
axiA_awlock Output User lock type.
axiA_awcache[3:0] Output User memory type.
axiA_awqos[3:0] Output User quality of service.
axiA_awprot[2:0] Output User protection type.
Table 6. User Master Write Data Channel
Port Direction Description
axiA_wvalid Output User write valid.
axiA_wready Input User write ready.
axiA_wdata[31:0] Output User write data.
axiA_wstrb[3:0] Output User write strobe.
axiA_wlast Output User write last.
Table 7. User Master Write Respond Channel
Port Direction Description
axiA_bvalid Input User write respond valid.
axiA_bready Output User respond ready.
axiA_bresp[1:0] Input User write respond.

Table 8. User Master Read Address Channel
Port Direction Description
axiA_arvalid Output User read address valid.
axiA_arready Input User read address ready.
axiA_araddr[31:0] Output User read address.
axiA_arregion[3:0] Output User region identifier.
axiA_arlen[7:0]2 Output User burst length.
axiA_arsize[2:0] Output User burst size.
axiA_arburst[1:0] Output User burst type, INCR only.
axiA_arlock Output User lock type.
axiA_arcache[3:0] Output User memory type.
axiA_arqos[3:0] Output User quality of service.
axiA_arprot[2:0] Output User protection type.
Table 9. User Master Read Data Channel
Port Direction Description
axiA_rvalid Input User read valid.
axiA_rready Output User read ready.
axiA_rdata[31:0] Input User read data.
axiA_rresp[1:0] Input User read respond.
axiA_rlast Input User read last.
Table 10. User Slave Clock and Reset
Port Direction Description
io_ddrMasters_0_clk Input AXI master clock.
io_ddrMasters_0_reset Output AXI master active high reset.

AXI Master Interface

Table 11. User Slave Write Address Channel
Port Direction Description
io_ddrMasters_0_aw_valid Input User write address valid.
io_ddrMasters_0_aw_ready Output User write address ready.
io_ddrMasters_0_aw_payload_addr[31:0] Input User write address.
io_ddrMasters_0_aw_payload_id[7:0] Input User write address ID.
io_ddrMasters_0_aw_payload_region[3:0] Input User region identifier.
io_ddrMasters_0_aw_payload_len[7:0] Input User burst length.
io_ddrMasters_0_aw_payload_size[2:0] Input User burst size.
io_ddrMasters_n_aw_payload_burst[1:0] Input User burst type, INCR only.
io_ddrMasters_0_aw_payload_lock Input User lock type.
io_ddrMasters_0_aw_payload_cache[3:0] Input User memory type.
io_ddrMasters_0_aw_payload_qos[3:0] Input User quality of service.
io_ddrMasters_0_aw_payload_prot[2:0] Input User protection type.
io_ddrMasters_0_aw_payload_allStrb[2:0] Input User all strobe type.
Table 12. User Slave Write Data Channel
Port Direction Description
io_ddrMasters_0_w_valid Input User write valid.
io_ddrMasters_0_w_ready Output User write ready.
io_ddrMasters_0_w_payload_data[m:0] Input User write data.
The length is fixed at 128-bit.
io_ddrMasters_0_w_payload_strb[15:0] Input User write strobe.
io_ddrMasters_0_w_payload_last Input User write last.
Table 13. User Slave Write Respond Channel
Port Direction Description
io_ddrMasters_0_b_valid Output User write respond valid.
io_ddrMasters_0_b_ready Input User respond ready.
io_ddrMasters_0_b_payload_id[7:0] Output User respond ID.
io_ddrMasters_0_b_payload_resp[1:0] Output User write respond.

Table 14. User Slave Read Address Channel
Port Direction Description
io_ddrMasters_0_ar_valid Input User read address valid.
io_ddrMasters_0_ar_ready Output User read address ready.
io_ddrMasters_0_ar_payload_addr[31:0] Input User read address.
io_ddrMasters_0_ar_payload_id[7:0] Input User read address ID.
io_ddrMasters_0_ar_payload_region[3:0] Input User region identifier.
io_ddrMasters_0_ar_payload_len[7:0] Input User burst length.
io_ddrMasters_0_ar_payload_size[2:0] Input User burst size.
io_ddrMasters_0_ar_payload_burst[1:0] Input User burst type, INCR only.
io_ddrMasters_0_ar_payload_lock Input User lock type.
io_ddrMasters_0_ar_payload_cache[3:0] Input User memory type.
io_ddrMasters_0_ar_payload_qos[3:0] Input User quality of service.
io_ddrMasters_0_ar_payload_prot[2:0] Input User protection type.
Table 15. User Slave Read Data Channel
Port Direction Description
io_ddrMasters_0_r_valid Output User read valid.
io_ddrMasters_0_r_ready Input External memory read ready.
io_ddrMasters_0_r_payload_data[m:0] Output External memory read data.
The length is fixed at 128-bit.
io_ddrMasters_0_r_payload_id[7:0] Output External memory read ID.
io_ddrMasters_0_r_payload_resp[1:0] Output External memory read respond.
io_ddrMasters_0_r_payload_last Output External memory read last.
1 axiA_awlen always outputs 0, that is, a burst length of 1. This setting makes the, axiA channel compatible with AXI-Lite.
2 axiA_arlen always outputs 0, that is, a burst length of 1.This setting makes the, axiA channel compatible with AXI-Lite.