Supervisor Trap-Vector Base-Address Register (stvec): 0x305

The stvec register is a 32-bit read/write register that holds trap vector configuration, consisting of a vector base address (base).

31										2	1	0
base											Reserved

Bits	Field	Description	Single/Multi-Core	w/FPU	w/MMU
0-1	Reserved	N/A	N/A	N/A	N/A
2-31	base	Vector base address.	N/A	N/A	Read/Write