Gating SoC Reset

An active high io_asyncReset signal brings all the logic back to their known initial state across all clock domains of the Sapphire high-performance RISC-V SoC. For the reset timing diagram, refer to Figure 1. The io_asyncReset signal must be in active high during configuration mode and de-assert once the LPDDR4 controller calibration is completed. Efinix recommends gating the reset as shown in the following diagram.

The PLL locked signal must be sourced from the dedicated io_systemClk PLL. The user I/O refers to the user's self-controlled signal that is normally attached to an external GPIO switch. However, you can design this signal from another source using soft logic. All the associated signals used to generate the io_asyncReset must have active high attributes.