The sip register is a 12-bit read/write register containing information
on pending interrupts.
| 11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| Reserved |
SEIP |
Reserved |
STIP |
Reserved |
SSIP |
Reserved |
| Bits |
Field |
Description |
Single/Multi-Core |
w/FPU |
w/MMU |
| 0 |
Reserved |
Reserved. |
N/A |
N/A |
N/A |
| 1 |
SSIP |
Supervisor software interrupt pending. |
N/A |
N/A |
Read/Write |
| 2-4 |
Reserved |
Reserved. |
N/A |
N/A |
N/A |
| 5 |
STIP |
Supervisor timer interrupt pending. |
N/A |
N/A |
Read/Write |
| 6-8 |
Reserved |
Reserved. |
N/A |
N/A |
N/A |
| 9 |
SEIP |
Supervisor external interrupt pending. |
N/A |
N/A |
Read/Write |
| 10-11 |
Reserved |
Reserved. |
N/A |
N/A |
N/A |