The following tables show the machine-level CSR implementation.
Table 1. Machine Information Register
| Address |
Register Name |
Privilege |
Description |
Width |
| 0xF14 |
mhartid |
Read |
Hardware thread ID. |
32 |
Table 2. Machine Trap Registers
| Address |
Register Name |
Privilege |
Description |
Width |
| 0x300 |
mstatus |
Read/Write |
Machine status register. |
13 |
| 0x304 |
mie |
Read/Write |
Machine interrupt enable register. |
12 |
| 0x305 |
mtvec |
Read/Write |
Machine trap handler base address. |
32 |
Table 3. Machine Trap Handling Registers
| Address |
Register Name |
Privilege |
Description |
Width |
| 0x340 |
mscratch |
Read/Write |
Scratch register for machine trap handlers. |
32 |
| 0x341 |
mpec |
Read/Write |
Machine exception program counter. |
32 |
| 0x342 |
mcause |
Read |
Machine trap cause. |
32 |
| 0x343 |
mtval |
Read |
Machine bad address or instruction. |
32 |
| 0x344 |
mip |
Read/Write |
Machine interrupt pending. |
12 |