Custom Instruction Interface

The Sapphire high-performance RISC-V SoC supports a custom instruction interface so you can accelerate software functions with custom hardware logic. The custom instruction supports R-type instructions, which provides two registers (rs1 and rs2) to custom instruction processing logic and up to 1,024 IDs to perform different functions.

Table 1. Custom Instruction PortsWhere n is the core number (0, 1, 2, or 3).
Port Direction Description
cpun_customInstruction_cmd_valid Output Indicates that registers rs1 and rs2 are present and ready for processing.
cpun_customInstruction_cmd_ready Input Indicates that the custom processing logic is ready to process register rs1 and rs2 from the CPU.
cpun_customInstruction_function_id[9:0] Output Function id for the custom instruction.
cpun_customInstruction_inputs_0[31:0] Output Register rs1 for the custom instruction.
cpun_customInstruction_inputs_1[31:0] Output Register rs2 for the custom instruction.
cpun_customInstruction_rsp_valid Input Indicates that the custom instruction result is available.
cpun_customInstruction_rsp_ready Output Indicates that the CPU is ready to accept the custom instruction result.
cpun_customInstruction_outputs_0[31:0] Input Result of the custom instruction.

Figure 1. Custom Instruction Waveform