Boot Flow

For the boot flow of the Sapphire high-performance RISC-V SoC, refer to the following flow chart.

The configuration block starts offloading the RAM content, which is the bootloader by default, to the Sapphire SoC’s on-chip RAM after the device is powered up and goes through initialization sequences. Other interface blocks such as PLLs dedicated to the SoC, soft logic block, and GPIO configuration should be programmed at this stage. Additionally, the SPI controller is required to be included in the soft logic block of the bootloader.

The Sapphire High-Performance SoC runs its reset sequence once the io_asyncReset has been released from the soft logic block. Also, the CPU starts to execute the bootloader that allows the SPI controller to start the retrieval process of the RISC-V firmware binary from the SPI flash. The retrieved data is redirected and stored in the LPDDR4 memory. This looping process continues until the bootloader completes its task. Then, the CPU jumps to the LPDDR4 memory start address to start the program execution.