Functional Description

The hardened RISC-V SoC block (HRB) consists of 4 Vexriscv cores. Each core consists of a memory management unit (MMU) that handles all memory and caching operations associated with the processors. The core runs at 1.0 GHz and controls the following RISC-V extensions:
  • 32-bit integer (I)
  • Multiply (M)
  • Atomic (A)
  • Compressed (C)
  • Single and double precision floating-point (FD) instruction extensions

You can use custom instruction interfaces to execute self-defined operations and debug with a JTAG debug module that has 8 hardware breakpoints and complies with the RISC-V debug specifications.

The HRB provides 4-way 16 KB data and instruction cache(s) to accommodate data and instruction exchanges with the main memory.

Additionally, the HRB has a 16 KB on-chip RAM for multi-purpose usage, which, by default, holds the bootloader that retrieves 124 KB data from the SPI flash and transfers it to the main memory during HRB power-up. An interrupt controller is also available that serves as an auxiliary controller for the CLINT timer, 24 user interrupts, and 2 user timers. You can configure the priority between the interrupt devices using the Efinity RISC-V IDE software.

To interface with the LPDDR4 memory, the HRB provides an AXI4 full-duplex interface with a 512-bit data width, and together with a 128-bit data width AXI4 slave, allows you to connect to the direct memory access (DMA). However, the AXI slave can only access the LPDDR4 memory. The HRB further provides another 32-bit, 256 MB AXI4 master interface for communication with the logic from the FPGA core fabric.

You customize the Sapphire High-Performance RISC-V SoC using the IP Manager in the Efinity® software.

Figure 1. Sapphire High-Performance Hardened RISC-V Block Diagram