Resets

The Sapphire high-performance RISC-V SoC has a master reset signal, io_asyncReset that triggers a system reset. Your RTL design should hold io_asyncReset for a minimum of 3 high state cycles of io_systemClk to reset the whole SoC system completely. When you assert io_asyncReset, the SoC asserts:
  • io_systemReset, which resets the RISC-V processor and on-chip memory.
  • io_peripheralReset, which resets the APB3 peripherals and AXI4 master.
  • io_memoryReset, which resets the LPDDR4 memory controller's AXI interface.
  • io_ddrMasters_0_reset, which responds to the reset for AXI slave channel 0 and is synchronized to io_ddrMasters_0_clk.
  • io_cfuReset, which responds to the reset for custom instruction and is synchronized to io_cfuClk.

The SoC asserts the io_memoryReset, io_ddrMaster_0_reset, io_peripheralReset, io_cfuReset, and io_systemReset signals at the same time to allow the AXI slaves access to the AXI cross bar once the reset completes.

Once io_systemReset goes low, the user binary code is executed.

Figure 1. Reset Timing Diagram
Table 1. Reset Ports
Port Direction Description
io_asyncReset Input Active-high asynchronous reset for the entire system.
io_systemReset Output Synchronous active-high reset for the system clock (io_systemClk).
io_peripheralReset Output Synchronous active-high reset for the peripheral clock (io_peripheralClock).
io_memoryReset Output External memory reset source from the RISC-V SoC.
io_ddrMasters_0_reset Output Responds to the reset for the AXI slave.
io_cfuReset Output Synchronous active-high reset for the custom instruction clock (io_cfuClock).