Revision History
| Date | Version | Description |
|---|---|---|
| May 2023 | 1.5 | Added descriptions to re-ordering example tables. (DOC-1273) |
| February 2023 | 1.4 | Added in statements for DDR3, LPDDR3 and LPDDR2. (DOC-1140) Added
a note regarding the trace length from FPGA pad to DRAM pad in topic DQ, DQS, DM
termination. Update feature - Read levelling for LPDDR2 in
topic DDR Module Comparison. |
| July 2022 | 1.3 | The section on re-ordering DDR3 incorrectly mentioned LPDDR3. (DOC-852) |
| July 2022 | 1.2 | Added note about write leveling trace requirement. |
| June 2022 | 1.1 | Added information on which signals can be re-ordered. (DOC-799) |
| May 2020 | 1.0 | Initial release. |