| Core voltage VDD (mV) |
1500, 1350 |
1200, 1800 |
1200, 1800 |
| I/O voltage VDDQ/CA (mV) |
1500, 1350 |
1200 |
1200 |
| VREF DQ (mV) |
750, 675 |
600 |
600 |
| VREF CA (mV) |
750, 675 |
600 |
600 |
| Maximum frequency (DDR controller) |
533 Mhz, DDR1066 |
533 Mhz, DDR1066 |
533 Mhz, DDR1066 |
| Burst lengths |
4, 8 |
4, 8, 16 |
8 |
| Configuration |
x8, x16 |
x16, x32 |
x16, x32 |
| Address commands signals |
27 Pins |
14 Pins |
15 Pins |
| CA bus data rate |
Single |
Double |
Double |
| DQ bus data rate |
Double |
Double |
Double |
| Output drive strength (Ω) |
34.3, 40 |
34.3, 40, 48, 60, 80, 120 |
34.3, 40, 48 |
| CA training |
– |
– |
 |
| Write leveling |
 |
– |
 |
| Read leveling |
 |
 |
 |
| Pre-bank refresh |
 |
 |
 |
| Output driver |
SSTL_15, SSTL135 |
SSTL_12 |
SSTL_12 |
| ODT |
 |
– |
 |
| Package option |
Discrete |
Discrete |
Discrete |