Differential Pair Skew

For correct DRAM operation, the timing of the DQS and CK differential pairs is critical. Efinix® strongly recommends that you match the electrical length between these legs and keep any differences to less than 5 ps.

Skew between the differential pair lines (intra-pair skew) impacts the monotonicity of the CK/CK# and DQS/DQS# signals, which are critical to the timing. Skew on these signals causes signal distortion and increases the bit error rate.

Figure 1. Effect of Intra-Pair Skew on Eye Diagram

Note: The Trion® DDR DRAM controller cannot deskew the differential signals. The zero crossing of the differential signals can seriously impact timing margins, leading to high jitter, high SNR, and increased sample errors.

Table 1. Trace Length's Effect on Signal Integrity
Property	Pin Match	Pin Mismatch
Length	< ±5% of trace length	> ±5% of trace length
Skew	< ±5ps	> ±5 ps
Delay	No skew	Skew
Jitter	Low	High
Sample error	Low	High
SNR	Low	High
Distortion	Low	High