Routing DDR Signals

  • Minimize PCB layer propagation variance.
  • Avoid T junctions for high-speed signals.
  • Meet all delay matching requirements for PCB trace delays, different layer propagation velocity variances, and crosstalk.
  • Surround the DRAM module's BGA pads with ground.
  • To minimize the return path:
    • For the byte lanes, match all DQ and DQS traces to within ±50 mils.
    • Route data groups next to a VSS plane.
  • Avoid placing high-speed DQ, DQS, address, and control signal across split planes. See Split Planes and Reference Planes for details.
  • Use a gradual trace angle to reduce parasitic effects (avoid 90° trace angles). See Bending Traces for details.

Clock Signals

The DDR DRAM modules require different master CLK and nCLK clock inputs. All CA input signals are sampled on both the rising and falling edges of CLK. The address and control signals are only sampled on the rising edge of CLK. The CS and CKE input signals are sampled on the rising edge of CLK.

  • Ensure the DDR DRAM modules have a clean differential clock input.
  • Balance the output data so that each data word has the same valid time as all of the signals.
  • Match the CK trace length to the CK# trace length ±20 mils. If multiple clock pairs are transmitted from the controller to components, all clock-pair traces should be equivalent within ±20 mils.
  • Efinix recommends using a stripline design for high-speed signals. See Microstrip and Stripline Skew for details.
Important: If you use the write leveling feature, the CK(n-1) trace length must be longer than the DQS(n-1) trace length. n is the number of DDR modules used. Refer to Table 1 for more skew control recommendations.