This section describes the recommended clock circuits to connect the RTT resistor to the
DDR clock pin termination. Placing the RTT resistor close to the DRAM clock pins
improves high-speed signaling and reduces the signal-to-noise (SNR) ratio.
Figure 1. Double Resistor Clock Termination
Table 1. Clock Design (CK, CK#) Requirements
PCB Design
Requirements
Differential impedance
100 Ω ± 10%
Routing spacing (other signals)
> 3 times the trace width
Trace width
> 4 mils
L1 + L3
< 7 inches (as short as possible)
L2 + L4
< 7 inches (as short as possible)
Maximum allowed vias
2
RTT0 and RTT1 resistors
50 Ω ± 5% recommended
CTT capacitor
0.1 μF recommended
Figure 2. Single Resistor Clock Termination
Table 2. Clock Design (CK, CK#) Requirements
PCB Design
Requirements
Differential impedance
100 Ω ± 10%
Routing spacing (other signals)
> 3 times the trace width
Trace width
> 4 mils
L1 and L2
Each < 7 inches (as short as possible)
Maximum allowed vias
2
RTT resistor
100 Ω recommended
