Introduction
- DDR Module Comparison
- Trion FPGAs with DDR DRAM
General Guidelines
Routing DDR Signals
Re-Ordering DQS, DQ, and DM Signals
- Re-Ordering for LPDDR3 and LPDDR2
- Re-Ordering for DDR3
Terminating Signals
Laying Out Traces
Controlling Skew
- Microstrip and Stripline Skew
- Differential Pair Skew
Controlling Impedance
Revision History

Trion FPGAs with DDR DRAM

Table 1. DDR DRAM Widths Supported for FPGAs and Packages
FPGA	Package	DDR DRAM Support	DQ Widths
T20, T35	BGA324	1 block	x8 or x16
T20, T35	BGA400	1 block	x8 or x16
T55, T85, T120	BGA324	1 block	x16
	BGA484	1 block	x16 or x32
	BGA576	1 block	x16 or x32

Parent topic: Introduction