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Introduction
DDR Module Comparison
Trion FPGAs with DDR DRAM
General Guidelines
Routing DDR Signals
Re-Ordering DQS, DQ, and DM Signals
Re-Ordering for LPDDR3 and LPDDR2
Re-Ordering for DDR3
Terminating Signals
DDR Clock Termination
DQ, DQS, DM Termination
DDR Address and Control Termination
Laying Out Traces
Maximum Trace Length
Trace Spacing
Bending Traces
Differential Pair Symmetry
Match Trace Lengths
Split Planes and Reference Planes
Fly-By Layout For Multiple DRAM Modules
Controlling Skew
Microstrip and Stripline Skew
Differential Pair Skew
Controlling Impedance
Revision History
Terminating Signals
DDR Clock Termination
DQ, DQS, DM Termination
DDR Address and Control Termination