DDR Address and Control Termination

The following terminations must be terminated on the circuit for the DDR address and control signals:
  • DDR3—A[15:0], nCS, nRAS, nCAS, nWE, BA[2:0], CKE, and ODT
  • LPDDR3—A[9:0], nCS, CKE, and ODT
Efinix recommends the termination of LPPDDR2 CK and ADDR for better signal integrity.
  • LPDDR2—A[9:0], nCS, CKE
Figure 1. DDR Address and Control Signal Circuit
Table 1. DDR Address and Control Design Requirements
PCB Design Requirements
Impedance 50 Ω ± 10%
Routing spacing (other signals) > 3 times the trace width
Trace width > 4 mils
RTT0 40 Ω ± 5% (recommended)
L1 + L3, L1 + L2 maximum length < 7 inches (as short as possible)
Maximum allowed vias 4