Introduction
- DDR Module Comparison
- Trion FPGAs with DDR DRAM
General Guidelines
Routing DDR Signals
Re-Ordering DQS, DQ, and DM Signals
- Re-Ordering for LPDDR3 and LPDDR2
- Re-Ordering for DDR3
Terminating Signals
Laying Out Traces
Controlling Skew
- Microstrip and Stripline Skew
- Differential Pair Skew
Controlling Impedance
Revision History

Trace Spacing

When planning your board's signal traces, maintain the correct spacing between traces. The minimum trace width for all DDR signals is 4 mils.

Figure 1. Trace Spacing Guidelines