DQ, DQS, DM Termination

This section describes the recommended circuit for the DQ, DQS, and DM signals.

Figure 1. DQ, DQS, and DM Connection between DRAM and FPGA
Note: Efinix recommends a serial termination be used if the trace length from the FPGA pad to the DRAM pad is more than (>) 5cm.
Figure 2. DQ, DQS, and DM Termination

Table 1. DQ, DQS, and DM Design Requirements
PCB Design Requirements
Impedance (DQ, DM) 50 Ω ± 10%
Differential impedance (DQS) 100 Ω ± 10%
Routing spacing (other signals) > 3 times the trace width
Trace width > 4 mils
RTT0 15 Ω ± 5% (recommended)
L1 maximum length DQ, DM: < 5 inches (as short as possible)
DQS: < 7 inches (as short as possible)
Maximum allowed vias 4