• Introduction
    • DDR Module Comparison
    • Trion FPGAs with DDR DRAM
  • General Guidelines
  • Routing DDR Signals
  • Re-Ordering DQS, DQ, and DM Signals
    • Re-Ordering for LPDDR3 and LPDDR2
    • Re-Ordering for DDR3
  • Terminating Signals
    • DDR Clock Termination
    • DQ, DQS, DM Termination
    • DDR Address and Control Termination
  • Laying Out Traces
    • Maximum Trace Length
    • Trace Spacing
    • Bending Traces
    • Differential Pair Symmetry
    • Match Trace Lengths
    • Split Planes and Reference Planes
    • Fly-By Layout For Multiple DRAM Modules
  • Controlling Skew
    • Microstrip and Stripline Skew
    • Differential Pair Skew
  • Controlling Impedance
  • Revision History

Maximum Trace Length

Efinix recommends using shorter traces, which results in better timing and makes it easy to deskew using DDR DRAM module leveling. Refer to these topics for specific requirements:
  • DQ, DQS, DM Termination
  • DDR Address and Control Termination
  • DDR Clock Termination