SDRAM Controller Testbench

You can choose to generate the testbench when generating the core in the IP Manager Configuration window. To generate testbench, the Testbench Deliverables Option signals must be enabled.

Note: You must include all .v files generated in the /Testbench directory in your simulation.

Important: tested the testbench generated with the default parameter options only.

provides a simulation script for you to run the testbench quickly using the Modelsim software. To run the Modelsim testbench script, run vsim -do modelsim.do in a terminal application. You must have Modelsim installed on your computer to use this script.

The testbench generates a clock signal, reset signal and memory model instantiation (generic_sdr.v). By default, the testbench runs with the AXI4 interface example design. If you want to run the native interface example design, change the module instantiation inside the testbench file.

The system displays the following error message if an error occurred:

ERROR: [8] READ DATA AAh is not the same as EXPECTED DATA BBh

Note: If you want to use your own testbench file, add the following line in your testbench file:

`define RTL_SIM