Ports

Table 1. SDRAM Controller Core Native Interface Ports
m = ba_width + row_width + col_width
n = Data rate * dq_group * dq_width
Port Direction Description
i_arst Input Positive controller reset.
i_sysclk Input Controller clock.
i_sdrclk Input Maps the tSU and tWD clocks to the following frequency:
  • i_sysclk—for full-rate (Data rate=1)
  • i_sysclk x2—for half-rate (Data rate=2)
i_tACclk Input Maps the tAC clocks to the following frequency:
  • i_sysclk—for full-rate (Data rate=1)
  • i_sysclk x2—for half-rate (Data rate=2)
200 MHz is sufficiently slow to share both i_sdrclk and i_tACclk with the same clock without getting errors in readback. Use the phase shift to adjust the access time if an error occurs.
i_pll_locked Input Assert when the PLL of i_sdrclk is locked. The clock is stable, and the SDRAM controller starts the SDRAM initialization sequence.
i_we Input Write enable. Write enable can be kept high throughout the required burst length to perform a burst write. Write enable can only be de-asserted if i_last is asserted and o_wr_ack is sampled as high.
i_re Input Read enable. Read enable can be kept high throughout the required burst length to perform a burst read. Read enable can only be de-asserted if i_last is asserted and o_rd_ack is sampled as high.
i_last Input Set to high to indicate the last transfer to terminate a burst write or read.
i_addr [m-1:0] Input SDRAM physical address mapped in the following physical address:
MSB LSB
Bank Row Column
  • Full-rate—all the column bits are valid.
  • Half-rate—the column LSB is ignored. The address must be in the increment of two.
i_din [n-1:0] Input Data to be written to SDRAM.
i_dm [n/8-1:0] Input Data mask per data byte.
o_dout [n-1:0] Output Data read from SDRAM. o_dout shares the same data address mapping as i_din.
o_sdr_init_done Output Indicates that the SDRAM initialization sequence is done and the SDRAM is ready.
o_wr_ack Output Write acknowledge. Handshaking with write enable.
o_rd_ack Output Read acknowledge. Handshaking with read enable.
o_rd_valid Output Read valid. The data on o_dout is valid to be read.
Table 2. SDRAM Controller Core AXI4 Interface Ports
m = ba_width + row_width + col_width
n = Data rate * dq_group * dq_width
Port Direction Description
o_AXI4_AWREADY Output The controller is ready to accept an address and associated control signals.
i_AXI4_AWADDR [m-1:0] Input Address of the first transfer in a write burst transaction mapped in the following physical address:
MSB LSB
Bank Row Column
Full-rate: All column bits are valid.
Half-rate: The column LSB is ignored. The address must be in the increment of two.
i_AXI4_AWVALID Input Master signaling valid write address and control information.
o_AXI4_WREADY Output The controller can accept the write data.
i_AXI4_WDATA [n-1:0] Input Write data.
i_AXI4_WLAST Input The last transfer in a write burst.
i_AXI4_WVALID Input Valid write data and strobes are available.
o_AXI4_BVALID Output Controller signaling a valid write response.
i_AXI4_BREADY Input Master can accept a write response
o_AXI4_ARREADY Output Controller ready to accept an address and associated control signals.
i_AXI4_ARADDR [m-1:0] Input
The address of the first transfer in a read burst transaction mapped in the following physical address:
MSB LSB
Bank Row Column
Full-rate: All column bits are valid.
Half-rate: The column LSB is ignored. The address must be in the increment of two.
i_AXI4_ARVALID Input Master signaling valid read address and control information.
i_AXI4_RREADY Input Master can accept the read data.
o_AXI4_RDATA [n-1:0] Output Read data.
o_AXI4_RLAST Output The last transfer in read burst.
o_AXI4_RVALID Output Valid read data and strobes are available.
i_AXI4_WSTRB [(n/8)-1:0] Input Write strobe signal per data byte.
i_AXI4_AWID [3:0]1 Input Write address ID.
i_AXI4_AWLEN [7:0]1 Input Write burst length.
The AXI write burst cannot crosses memory column address boundary.
For example, if the column width = 8, 8'hFF, the last write burst need to happen at column address 8'hFF.
o_AXI4_BID [3:0]1 Output Respond ID.
i_AXI4_ARID [3:0]1 Input Read address ID.
i_AXI4_ARLEN [7:0]1 Input Read burst length.
i_AXI4_RID [3:0]1 Input Read ID.
1 Applicable to AXI4 full mode only.