Features

• Fully parameterized to be compatible with any SDRAM device
• Native mode or Advanced eXtensible Interface 4 (AXI4) mode user interface
• Half-rate or full-rate
• Memory burst length of 1
• Bank interleaving
• Random access within the same row
• Column access strobe (CAS) latency of 2 or 3
• Verilog HDL RTL and simulation testbench
• Includes an example design targeting the Trion® T20 BGA256 Development Board