Native Write Timing

Figure 1. Native Write Timing Waveform
  1. Master asserts write enable signal with both valid address and data. Master waits for the write acknowledgement from the SDRAM controller.
  2. SDRAM controller acknowledges to the write enable signal.
  3. Master updates the next address and data. Write enable signal remains high for a burst write.
  4. Master terminates the burst write by asserting last signal.
  5. Master de-asserts write enable and last signals.