SDRAM Controller Example Design

You can choose to generate the example design when generating the core in the IP Manager Configuration window. Compile the example design project and download the .hex or .bit file to your board. To generate example design, the Example Design Deliverables Option signal must be enabled.

Important: tested the example design generated with the default parameter options only.

The example design targets the Trion® T20 BGA256 Development Kit. This design continuously writes to the memory with counting up data pattern. After 255 bursts of write data are written to the memory through the AXI4 interface, the design reads back all the data with a burst read operation. The comparator in the design compares the read back data with the expected write data. You can observe the following board LED behaviours:

  • LED D4 and D5 blink when there is an error.
  • LED D3 blinks and LED D8, D9, D10 light-up when there is no error.
To reset, press push button SW4.
Figure 1. Example Design Block Diagram
  • Test Stimulus—Perform write burst and read burst operations.
  • Comparator—Compares the written and read back data from the memory.
  • Logic Analyzer—Debug core used to perform manual calibration shown in Manual Calibration.
Table 1. Example Design Implementation
FPGA Interface LUTs Memory Blocks fMAX (MHz)1 Efinity® Version
T20 BGA256 C4 Native 5,578 64 118 2019.3
AXI4 5,700 65 123
1 Using default parameter settings.
2 Using Verilog HDL.