Manual Calibration

Due to the tCO of the SDRAM and the printed circuit board (PCB) trace delay, you must perform a manual calibration once per system for the SDRAM controller to work properly.

tACclk Phase Shift Alignment

Align the tACclk phase shift to the center of access window of read data sample time.

Figure 1. tACclk Read Memory Operation

tIORT Parameter Alignment

Adjust the tIORT to align the tCO of SDRAM and PCB trace delay. The tIORT value is determined by the following equation:

tIORT = (PCB trace delay output + tCO + PCB trace delay input) / i_sysclk period

Figure 2. tIORT Dependence