Memory Interface

Table 1. SDRAM Controller Memory Interface PortsRefer to Memory Interface Connection Settings for more information about connecting the memory interface ports.
Port Direction Width Description
o_sdr_CKE Output Data rate SDRAM CKE pin.
o_sdr_n_CS Output Data rate SDRAM #CS pin.
o_sdr_n_RAS Output Data rate SDRAM #RAS pin.
o_sdr_n_CAS Output Data rate SDRAM #CAS pin.
o_sdr_n_WE Output Data rate SDRAM #WE pin.
o_sdr_BA Output Data rate * ba_width SDRAM BA pins.
o_sdr_ADDR Output Data rate * row_width SDRAM ADDR pins.
o_sdr_DATA Output Data rate * dq_group * dq_width SDRAM DQ pins from FPGA to SDRAM.
o_sdr_DATA_oe Output Data rate * dq_group * dq_width SDRAM DQ output enable for I/O buffer.
i_sdr_DATA Input Data rate * dq_group * dq_width SDRAM DQ pins from SDRAM to FPGA.
o_sdr_DQM Output Data rate * dq_group SDRAM DQM pins.

Memory Interface Connection Settings

If your design uses the HARD ddio_type, set each of the memory interface ports in Interface Designer as follows:

  • Select resync for Double Data I/O Option
  • Connect the LSB half of the signal to Pin Name (HI)
  • Connect the MSB half of the signal to Pin Name (LO)

For design using SOFT ddio_type, the MSB half of the signal is invalid.